High speed and low power 8 bits- Dadda Multiplier using Square root Carry Select Adder with Binary to Excess one Converter

Recently many applications like image processing, image recognition and signal processing have created need to abate power consumption and improve processing speed. Since Multiplication is a basic arithmetic operation for various such applications, processor performance can be enhanced with a highly efficient multiplier circuit. Efficiency of the multiplier circuit can be improved by reducing the transistor count. In order to accomplish this, selecting a logic which gives the optimal solution plays a vital role. Implementation of Dadda multipliers will create a structure which consumes minimal power and operates at faster rate than any other multipliers. The Dadda tree reduction methodology is used in the Dadda multiplier to process the partial product and to get the final product. Partial product heights are reduced using half adders and full adders. In the final stage partial product will be reduced using a standard adder- square root carry select adder with binary to excess one converter to attain final product. Designing the entire circuit in pass transistor logic and including binary to excess one converter in square root carry select adder will reduce the transistor count, power consumption, propagation delay and area.