A Scalable Small-Footprint Time-Space-Pipelined Architecture for Reservoir Computing

Reservoir computing (RC) is a lightweight machine learning algorithm for edge applications, which features a lower computation workload and one-time training process compared with the recurrent neural network (RNN) and Transformer. The existing RC accelerators still suffer considerable hardware overhead, which cannot satisfy the scalability on various edge FPGA/ASIC resource limits. This brief proposes a scalable small-footprint time-space-pipelined architecture for the cycle RC paradigm. The RC workload can be distributed onto a configurable number of processing elements (PE) under scalable resource limits. A time-space-pipelined PE is designed to efficiently execute the cycle RC computation, with the power-of-2 piecewise linearization circuits for non-linear activation function. Experimental results show that the proposed architecture can match a large variety of FPGA resource limits and ASIC power/area limits, with
$12.6\times $
energy efficiency improvement compared with the state-of-the-art RC accelerator.