A New Data Fitting Method for Parasitic Impedances of Power Transistor Packages using Two-Port S-Parameter Measurements

The parasitic inductances, resistances and capacitances of power transistor packages play a vital role in power transistor applications. They lead to increased switching losses and longer switching transients, which is why it is pivotal to accurately assess these values. We present a new way of fitting these values from two-port S-parameter measurements. The result is a fully automated method with low computational effort and good accuracy. In this study 2 different packages have been investigated which were supplied by Infineon. The transistors were mounted on a specially designed PCB and measured with a network analyzer. The corresponding S-parameter files were then fed into a Matlab script which computed the reconstruction method. Furthermore, the effort and accuracy of this estimation are compared to other methods found in literature.