Lowering Latency in a High-Speed Gate-Level-Pipelined Single Flux Quantum Datapath Using an Interleaved Register File

In this paper, we successfully demonstrate the 50-GHz operation of a microprocessor datapath based on single-flux-quantum (SFQ) logic with a gate-level pipeline (GLP) structure. The microprocessor datapath features a register file (RF), an arithmetic logic unit (ALU), and a long feedback loop that connects these components. Interleaved data-processing is applied in the RF. As the operating frequency of the RF is half that of the ALU, the timing constraints are eased; thus, we can reduce the number of pipeline stages used for timing adjustments. We designed a 4-bit datapath using the proposed technique, targeting 50-GHz operation. Compared to the conventional datapath, the total number of pipeline stages and the latency decreased from 49 to 24 and from 980 to 760 ps respectively. We fabricated test chips using the AIST Nb 9-layer 10-kA/cm
$^{2}$
process, and performed successful on-chip high-speed tests. In addition, our preliminary experiments suggest that we can expect 1.6-fold higher throughput at an 80-GHz clock frequency, at the cost of a 10% increase in latency.