Investigation Into Active Gate-Driving Timing Resolution and Complexity Requirements for a 1200 V 400 A Silicon Carbide Half Bridge Module

Silicon Carbide MOSFETs have lower switching losses when compared to similarly rated Silicon IGBT, but exhibit faster switching edges, larger overshoots and increased oscillatory switching behaviour, resulting in greater electro-magnetic interference (EMI) generation. Active Gate Drivers (AGD) can help mitigate these issues while maintaining low switching losses. Numerous AGD topologies have been presented with varying capabilities in terms of timing resolution and output stage complexity. This paper presents an experimental investigation into the influence these capabilities have on the switching performance of an AGD driven high current module, with the goal of advising future AGD designers on the performance trade-offs between signal resolution and complexity. A 2.5 ns resolution 6-level AGD was utilised in combination with parameter sweeps and a genetic algorithm to determine gate voltage patterns that provided improved switching performance. Results indicate that higher resolution (2.5–5 ns) provided the greatest improvements in switching performance, even utilising the simplest considered gate driving patterns, with the use of more complex patterns offering minimal additional improvements. However, at lower timing resolutions (10–40 ns) a stronger set-point dependence degradation in switching performance is observed when using simpler gate patterns, which can be mitigated by utilising more complex patterns.