VLSI Hardware Architecture of Neural A* Path Planner

Path planning is an elemental and critical task in modern autonomous systems. Recently, Neural
$\mathbf{A}^{\ast}$
, a data-driven neural planner reformulated from the
$\mathbf{A}^{\ast}$
search algorithm, has been proposed with high performance. However, because the path search procedure of the Neural
$\mathbf{A}^{\ast}$
path planner is mainly composed of matrix operations, such computation-intensive nature poses severe challenges for deployment on the time-constrained power-constrained embedded platforms. In this paper, we propose an efficient hardware architecture for the Neural
$\mathbf{A}^{\ast}$
path planner with specifically path search scheme. The hardware accelerator is implemented and synthesized using CMOS 28nm technology. Evaluation result shows the proposed hardware design achieves order-of-magnitude increase over CPU and GPU implementations with respect to area efficiency and energy efficiency.