Design of Operational Transconductance Amplifier using gm/Id method in 180nm Technology

The reduction in transistor size has led to the failure of the conventional square-law devices in describing the Short Channel and Moderate Weak inversion devices. The shortcomings of these devices are addressed by the gm/Id method that traverses between the hand calculations and circuit simulation. In this literature, a structured process for the design of a Two-Stage Operational Transconductance Amplifier is presented. The graphical approach is used to investigate the link between transconductance by current versus normalized drain current. The geometry of the transistors is calculated from the graph. The Operational Transconductance Amplifier is designed using 180 nm Predictive Technology Model using various parameters like Slew Rate, DC Open-Loop Gain, Common-Mode Rejection Ratio, Input Range, and Output Range. In this paper, the Two-Stage Operational Transconductance Amplifier gives 55 dB gain and 220 µW of power consumption.