A Low-Latency Dual-Path QC-LDPC Decoder for IEEE 802.11ax

Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes have been widely adopted to achieve excellent error correction performance in many wireless communication systems. The growing use of QC-LDPC codes calls for a low-latency and low-complexity decoder architecture that can be used in practical baseband chips. This paper presents a fully compatible low-latency LDPC decoder for IEEE 802.11ax. In contrast to the traditional partially parallel structure, such as the row parallel or block serial, we propose a scheme to realize the parallel of double blocks with few stall cycles. The first part of the strategy is to obtain the optimal sub-matrix prototypes, H_p1, H_p2, and corresponding access order offline. The second part is to decode according to the specified order. Besides, the related pipelined successive processing hardware is also designed with a memory bypass strategy. The proposed decoder is implemented in a 55 nm process with 482K logic gates, a throughput of 2132 Mbps, and a single iteration clock cycle of 45-63. Compared to other decoders with similar parallelism, this decoder stands out in terms of latency, hardware complexity, and energy efficiency.