Design and Comparative analysis of 6T and 7T SRAM Cells for Improved TREAD and TWRITE Noise Margins

SRAM (static random-access memory) is used to store the cache memory or data in static form. Unlike DRAM (dynamic random-access memory) it needs not to be refreshed. SRAM gives faster access than DRAM and it retains data bits as long as power is being supplied. DRAM uses capacitor to store the data bits whereas SRAM uses latching circuit(flip-flop). The latching circuit consists of four transistors (two CMOS inverters which are cross coupled) act as memory part. This paper compares 6T and 7T SRAM using Tanner EDA tools on 45nm technology. For both SRAMs, all the parameters such as Read noise margin, W-rite noise margin, and Hold noise margin are calculated and compared at different cell ratios. In our simulation we found that 7T SRAM cells have a larger noise margin than 6T SRAM cells at the same cell ratio, and as the cell ratio increases noise margins also increase.