FSM Based DNA Assembly Using Systolic Array

In this paper, we investigate the feasibility of computing DNA patterns on FPGAs by utilising high-performance and parallel computing. In particular, the report analyses and contrasts the FSM -based core implementation of the well-known Smith-Waterman pair-wise sequence alignment algorithm with the dynamic and heuristic alternatives that are currently on the market. In this research project, we investigate the use of parallel and high-performance computing to determine how DNA patterns can be computed on FPGAs. In particular, the report details the findings of a study that compared the FSM -based core implementation of the well-known Smith-Waterman pair-wise sequence alignment algorithm with the algorithm's current dynamic and heuristic programming methods. The study was carried out by comparing these three aspects of the algorithm. The traditional methods of sequence alignment that are software-implied are not adequate to meet the actual data rate requirements. A strategy that is based on the use of hardware makes it possible to process multiple new databases in parallel, which enables a high degree of scalability. A finite state machine serves as the primary data processor in our demonstration of how to organize the sequences of amino acids in a protein (FSM). We also investigate the effectiveness of bit-based sequence alignment algorithms and present the inner stage pipelined FPGA architecture for implementing sequence alignment. Both of these are presented in this paper. Synchronized controllers are utilized in the programming techniques of the algorithm for the purpose of parallel sequence alignment. Inference is the foundation of traditional software-based methods for sequence alignment, but these methods are unable to keep up with the required data rates. A strategy that is based on hardware allows for the processing of parallel tasks with a large number of new databases and provides excellent scalability. Our explanation of the classification of protein sequences is based on a Finite State Machine, which serves as the primary processing unit (FSM). In addition to this, we investigate how well bit-based sequence alignment algorithms work and present the inner stage pipelined Field Programmable Gate Array architecture that can be used to implement sequence alignment. Synchronized controllers are utilized in the process of performing sequence alignment in parallel. The architecture as a whole was made to be scalable and fast, with a small number of computations and the ability to perform parallel processing in hardware using field-programmable gate arrays to compare bits in patterns. Finally, we use FPGA hardware synthesis to show off impressive performance and low resource consumption.