Power Estimation Tool for Divider Generator IP Core Based on Xilinx Zynq SOC

Division is one of most complex arithmetic operation as compared to other arithmetic operations in processor architectures. In any algorithm, the designers' primary goal is to reduce the number of divisions. There are various division algorithms are available in literature that focuses on optimal solution for latency and throughput. Moreover, the hardware solution also focuses on the resources utilized. Xilinx divider generator IP core provides three different algorithms that trade-offs among latency, throughput and resources utilized. However, the power estimation of these algorithms is missing in the datasheet. Therefore, this paper implements early power estimation model for Radix-2 non-restoring algorithm for divider generation IP core 5.1 targeted to Zed Board based on Xilinx Zynq SOC. The model has been developed using supervised machine learning regression and curve fitting. Using the Vivado design suite IP core tool, many division generator setups with varied I/O vector lengths are created. The power has been estimated using the proposed model and validated using Vivado Power Estimation and Analysis Tools. The proposed power estimation model is highly accurate as it provides an average error of 1.76% only.