ESnet/JLab FPGA Accelerated Transport

To increase the science rate for high data rates/volumes, Thomas Jefferson National Accelerator Facility (JLab) has partnered with Energy Sciences Network (ESnet) to define an edge to compute cluster traffic shaping/steering transport capability featuring data event aware network shaping and forwarding. The keystone of this ESnet+JLab field programmable gate array (FPGA) accelerated transport (EJFAT) is the joint development of a dynamic compute work load balancer (LB) of UDP streamed data. The LB is a suite consisting of a FPGA executing the dynamically configurable, low fixed latency LB
data plane
featuring real-time packet redirection and high throughput, and a
control plane
running on the FPGA host computer that monitors network and compute farm telemetry in order to make dynamic load-balancing decisions for destination compute host redirection/load balancing. The LB provides for three-tier horizontal scaling across LB suites, cluster compute hosts, and CPUs within a host. The LB effectively provides seamless integration of edge/cluster computing to support direct experimental data processing for immediate use by JLab science programs and others such as the electron-ion collider (EIC) as well as data centers of the future requiring high throughput and low latency for both time-critical (e.g., data acquisition systems) and data-driven (data center) workflows.