A High-Linearity 10-GHz-ERBW 3-to-7-GS/s Voltage-to-Time Converter with Built-In S/H

This paper discusses a linear, high-speed voltage-to-time converter (VTC) as the front end in a time-based analog to-digital converter (TB-ADC). The VTC architecture is based on a constant-slope charging technique with an inherent sampleand-hold stage and adjustable output delay range, capable of up to 7-GS/s conversion rate. The design in implemented in a 65-nm TSMC CMOS process and measured results at 3, 5, and 7GS/s are presented. At 7GS/s, the VTC has a max. output differential delay range of 33 ps, ENOB of 5. lbits (at low input frequencies), and the VTC core consumes 9. 0mW. The input effective resolution bandwidth (ERBW) of this VTC makes it capable of wideband conversion, with a maximum ERBW of greater than 10 GHz measured at 3 GS/s. Time-domain measurements of the VTC are also discussed.