The grid bus architecture for MIMD

An MIMD computer interconnection architecture, the grid bus architecture, is explored. Algorithms are introduced which route messages in an efficient and fault-tolerant manner. A chip which implements the basic algorithm was built to show how the algorithm can be designed into hardware. Simulations of the architecture show the decrease in performance under high loads and larger array sizes. Other simulations show the good performance of the fault-tolerant algorithms in this system. Some of the methods discussed can be applied to some similar architectures, such as the spanning-bus hypercube and other hypercube architectures.<
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