Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction

Analog integrated circuit (IC) placement is a heavily manual and time-consuming task that has a significant impact on chip quality. Several recent studies apply machine learning (ML) techniques to directly pre-dict the impact of placement on circuit performance or even guide the placement process. However, the significant diversity in analog design topologies can lead to different impacts on performance metrics (e.g., common-mode rejection ratio (CMRR) or offset voltage). Thus, it is unlikely that the same ML model structure will achieve the best performance for all designs and metrics. In addition, customizing ML mod-els for different designs require more tremendous engineering efforts and longer development cycles. In this work, we leverage Neural Ar-chitecture Search (NAS) to automatically develop customized neural architectures for different analog circuit designs and metrics. Our pro-posed NAS methodology supports an unconstrained DAG-based search space containing a wide range of ML operations and topological con-nections. Our search strategy can efficiently explore this flexible search space and provide every design with the best -customized model to boost the model performance. We make unprejudiced comparisons with the claimed performance of the previous representative work on exactly the same dataset. After fully automated development within only 0.5 days, generated models give 3.61 % superior accuracy than the prior art.