Approximating HW Accelerators through Partial Extractions onto shared Artificial Neural Networks

One approach that has been suggested to further reduce the energy consumption of heterogenous Systems-on-Chip (SoCs) is approxi-mate computing. In approximate computing the error at the output is relaxed in order to simplify the hardware and thus, achieve lower power. Fortunately, most of the hardware accelerators in these SoCs are also amenable to approximate computing. In this work we propose a fully automatic method that substitutes portions of a hardware accelerator specified in C/C++/SystemC for High-Level Synthesis (HLS) to an Artificial Neural Network (ANN). ANNs have many advantages that make them well suited for this. First, they are very scalable which allows to approximate multiple separate portions of the behavioral description simultaneously on them. Second, multiple ANNs can be fused together and re-optimized to further reduce the power consumption. We use this to share the ANN to approximate multiple different HW acceler-ators in the same SoC. Experimental results with different error thresholds show that our proposed approach leads to better results than the state of the art.