Automatic Generation of Complete Polynomial Interpolation Design Space for Hardware Architectures

Hardware implementations of elementary functions regularly de-ploy piecewise polynomial approximations. This work determines the complete design space of piecewise polynomial approximations meeting a given accuracy specification. Knowledge of this design space determines the minimum number of regions required to approximate the function accurately enough and facilitates the generation of optimized hardware which is competitive against the state of the art. Designers can explore the space of feasible architec-tures without needing to validate their choices. A heuristic based decision procedure is proposed to generate optimal ASIC hard-ware designs. Targeting alternative hardware technologies simply requires a modified decision procedure to explore the space. We highlight the difficulty in choosing an optimal number of regions to approximate the function with, as this is input width dependent.