Demonstration of Order Statistics Based Flash ADC in a 65nm Process

This paper presents measurement results of a flash ADC that uti-lizes offset voltages as references. To operate the minimum number of comparators, we select the target comparators based on the rankings of the offset voltage. We present performance improvement by tuning offset voltage distribution using multiple comparator groups under the same power. A test chip in a commercial 65 nm GP process demonstrates the ADCs at 1 GS/s operation.