A Two-Stage Low-Noise Amplifier with Extra Capacitor Structures for Low-Power Applications

A two-stage low-noise amplifier (LNA) with high performance successfully implemented in a 0. 18μm CMOS process is presented. The input and noise matching networks and overall power consumption can be improved by adopting extra capacitors connected between gate and source terminals of transistors. Around 3 GHz, the proposed two-stage LNA has the features, such as a noise Figure (NF) of 5.9 dB, a peak gain of 15.2 dB, an input third-order intercept point (IIP3) of -8dBm, an input 1-dB compression point (P
1dB
) of -17.5 dBm, respectively. From a 1.2 V supply, the proposed two-stage LNA consumes the 6mW.