Analytical Modeling of Ground Noise Induced Jitter in CMOS Inverters

This study proposes an analytical method for estimating jitter in CMOS inverters due to the ground noise (ground-bounce noise). The equations for modeling the transition edge of output response based on device parameters have been derived for both the cases with and without considering the effects of ground noise. The timing deviation in the transition edge of the output signal with respect to its ideal position is analytically derived. Two different technology nodes (65 nm and 180 nm) of United Microelectronics Corporation (UMC) are used to validate the proposed methodology. The proposed methodology yields results that are quite well matched with those obtained using an electronic design automation (EDA) tool.