Optimization of Ge Gate All Around Field-Effect Transistors at a deca-nm node for Low Power Applications

Device scaling hit the brick wall due to short channel and quantum effects. At sub-deca nanometers, quantum mechanics begins to dominate over classical theory. The Gate All Around field effect transistor performance is compared with existing FinFET devices at sub 10 nm node to keep the Moore’s law alive. In this work, the modelling optimization for Sub 10nm, is performed for both device types. The performance was investigated by utilizing the device simulator (ATLAS) by Silvaco TCAD tool. All the simulations were performed by Bohr Quantum Potential (BQP) model, the energy-dependent model was used for electrons, and field-dependent mobility (FLDMOB) and Shockley-Read-Hall (SRH) recombination models were used for carriers. Fermi-Dirac statistics are used instead of Boltzmann statistics. The effect of the device architecture, oxide thickness, high-κ oxide, doping profiles and gate material on device performance were studied and a performance-based comparison of Fin-FET and GAA-FET has been computed. The GAA architecture was found superior in terms of suppressed short channel effects like reduced DIBL, reduced Subthreshold Swing, high gain and high ION/IOFF current ratio. A comparison of the square cross-sectional channel and circular cross-sectional channel GAAFETs reveals that the latter has further improved performance accounting for reduced corner effects and strong symmetry in volume inversion.