QuSAF: A Fast ATPG for SAFs in VLSI Circuits Using a Quantum Computing Algorithm

The gate count in semiconductor chips is overgrowing. On the contrary, the feature size of the chip is continuously decreasing, resulting in higher design complexity. Consequently, circuit components in chips are exposed to various faults. A stuck-at fault is mostly addressed in circuits. We need good test patterns that trigger the defects to test the stuck-at marks. In large combinational circuits, the search space for test patterns grows exponentially with the number of inputs. Therefore an efficient test pattern generation technique is needed. An ATPG method discussed in the literature provides a time complexity of O(n) or more with the search space size n. This paper presents a fast ATPG technique named "QuSAF" that employs a Quantum Computing algorithm (QCA). The proposed QuSAF technique converts ATPG into Boolean Satisfiability (SAT) and then solves the resultant SAT expression using Grover’s Search Algorithm (GSA). The proposed approach generates the test patterns for a circuit by $O\left( {\sqrt n } \right)$ time. Experiments are performed with various basic logic gates to show the effectiveness of the proposed technique.