Power Efficient Approximate Multiplier Architectures for Error Resilient Applications

New approximate unsigned multiplier architectures are suggested in this paper with the goal of achieving improved accuracy while consuming less area and power. In our proposed designs, the approximation is applied in partial product reduction (PPR) stage. In PPR, efficient approximate compressor is used to reduce the number of partial product rows. Further to improve the accuracy error correcting module is included in the reduction structure. Experimental results for the 8-bit multiplier design demonstrate improvements in power and power-delay product of 40.43% and 47.11% when the suggested design is compared to the exact design and 21.61% and 24.72% when compared to other approximate designs, respectively, without sacrificing accuracy.