A High-Frequency and Low-Jitter DLL With Quadrature Error and Duty-Cycle Corrections Based on Asynchronous Sampling

This letter presents a quadrature error and duty-cycle correction circuit based on an asynchronous sampling technique. Sampling the multiphased clocks provides their phase and duty-cycle information, which are then utilized to compensate for the quadrature and duty-cycle errors. The intrinsic downconversion operation of the proposed sampling approach enhances the correction accuracy by mitigating circuit mismatch effects. The quadrature-error corrector (QEC) and duty-cycle corrector (DCC) circuits receive control signals generated from the asynchronous phase detectors and correct the clock outputs accordingly. Combined with a delay-locked loop (DLL), the proposed design is fabricated in a 40-nm CMOS process, consumes 7.2 mW, and occupies 0.023 mm2. It achieves 0.837-ps RMS jitter and 1.68° maximum phase error from multiple chip samples.