Automatically Restructuring HDL Modules for Improved Reusability in Rapid Synthesis

Implementing nontrivial HDL designs can take a lot of time. Particularly for FPGAs, vendor tools tend to become slower, since the devices grow and thus, also the designs grow. It is therefore desirable to create mechanisms that speed up the implementation. Combining pre-implemented blocks to build the final design can be one such mechanism. It can help to reduce the time required for incremental builds, or it can reduce the time required to build families of designs. Yet, typical HDL code is not structured for this purpose. Many modules do not have the right size to be used as pre-implemented blocks. In this paper, we present a methodology to automatically analyze and modify existing HDL code such that the resulting module structure fits the purpose of pre-implementing the modules. To this end, we try to isolate parameters of the HDL code such that we have to reimplement only a small number of modules after a parameter change. The resulting tool is available as open-source software. We have tested our methodology using multiple different benchmark sets, which in total contain thousands of modules. On average, we can extract around 10% of the parameters into smaller modules.