An Improved Path Delay Variability Model via Multi-Level Fan-Out-of-4 Metric for Wide-Voltage-Range Digital CMOS Circuits

In advanced CMOS technology, process, voltage, and temperature (PVT) variations increase the paths' latency in digital circuits, especially when operating at a low supply voltage. The fan-out-of-4 inverter chain (FO4 chain) metric has been proven to be a good metric to estimate the path's delay variability, whereas the previous work ignored the non-independent characteristic between the adjacent cells in a path. In this study, an improved model of path delay variability is established to describe the relationship between the paths' max-delay variability and an FO4 chain, which is based on multilevel FO4 metric and circuit-level parameters knobs (i.e., cell topology and driving strength) of the first few cells. We take the slew and load into account to improve the accuracy of this framework. Examples of 28 nm and 40 nm digital circuits show that our model conforms with Monte Carlo simulations as well as fabricated chips' measurements. It is able to model the delay variability effectively to speed up the design process with limited accuracy loss. It also provides a deeper understanding and quick estimation of the path delay variability from the near-threshold to nominal voltages.