Hardware preprocessing for the H1-Level 2 neural network trigger upgrade

The H1-Level 2 neural network trigger has been running successfully at Deutsches Elektronen Synchrotron (DESY) for four years. In order to provide increased selectivity at the higher luminosity planned for the HERA upgrade, an improved "intelligent" preprocessing has been devised. This system extracts complementary physics information from the Level 1 trigger stream and furnishes it to the L2 neural network in order to improve its decision. A new preprocessing board (the Data Distribution Board Version 2-DDB2) is currently being designed at the Max Planck Institute for Physics, Munich, Germany, in order to implement the necessary algorithms in fast field programmable gate arrays (FPGA), taking advantage of parallelism and pipelined structures in order to meet the timing requirement of 8 /spl mu/s. We present the different algorithmic steps and report on the current status of the DDB2 hardware upgrade.