TSpice-Alecsis co-simulation

Tanner Tools system (TTS) is a very useful tool for design automation. However, during the layout verification phase, the overall circuit is flattened and only transistor level simulation by TSpice simulator is possible. Obviously, this is not convenient especially regarding large digital or mixed circuits. Therefore, this paper describes a methodology for joint simulation based on Alecsis mixed-mode circuit simulator. The method is described on example of 64-level Calibrated Current-steering DAC.