Low Power CMOS Comparator with low offset voltage and good resolution for 10-bit SAR ADC

In this research paper, a CMOS comparator has been designed using 180 nm technology node. The purpose of this design is to minimize the power consumption and reduce the offset voltage of the comparator block. An Analog to Digital Converter (ADC) designed with this designed comparator will be compatible with low-power applications and provide good resolution. The proposed comparator can also be used for detectors requiring high sensitivity.