Impact of Trap Charge effects on the Performance of 2D material-based FET

The work analyzed the electrostatic behavior of interface trap charge-induced two-dimensional material-based FET. An analytical surface potential model has been developed considering the existence of interface trap charges at the interface of the semiconductor material and the gate oxide. The experimental data has validated the developed model with satisfactory accuracy. The WSe
2
is chosen as the 2D material in this work. Furthermore, the proposed device’s intrinsic delay and power dissipation have been calculated. Finally, the device characteristics of the FET structure with and without trap charges along the circuit parameters, viz. intrinsic power, delay, and power-delay product (PDP), are compared in the work.