Performance Analysis of Adiabatic CMOS Interface for Low Power Applications

This paper presents a comparative analysis of Adiabatic and Standard CMOS Interface circuit, for minimizing the power dissipation. The main consideration is to compare the power dissipation of interfaces and optimum results should be obtained. The transient analysis in all the memory cells have been carried out. Furthermore, the variation of power dissipation with temperature and power supply have been investigated. The variation of power delay product with power supply has also been analyzed. The simulations are implemented in 65nm CMOS technology in TSPICE.