Impact of Single Defects on NBTI and PBTI Recovery in SiO2 Transistors

The reliable operation of MOS transistors is affected by charge trapping at defects located inside the oxide and at the oxide/semiconductor interface. Each of the single defects can capture and emit a charge, alter the device electrostatics and thus affect the device behavior, which can be observed as a drift of the threshold voltage. Understanding the physical mechanisms of charge trapping and the dependencies of the threshold voltage drifts on the device parameters is crucial for reliable operation of modern transistors and the implementation of future technology nodes. An enhanced understanding can be developed by performing electrical measurements on nanoscale devices which allow to detect discrete steps in the measured drain current which correspond to emission events of charges, previously captured at single defects. Using measurements on large sets of devices, statistical distributions of step heights can be created to study the dependence of statistical quantities, like the link between the average threshold shift of a single emission event and the lateral device dimensions. From our measurements on commercial pMOS and nMOS devices we found that the dependence of the average step height on $W \times \sqrt L $ allows to describe the data accurately for a wide range of gate widths and lengths while the most widely used dependence on the device area fails to provide a good agreement.