On-Chip Fast Signal Generation and Low-Power SAR ADC for SiPM Readout

This article presents an ON-chip fast signal generator and a successive-approximation-register (SAR) analog-to-digital data converter (ADC) for silicon photomultiplier (SiPM) readout applications. The high-pass filter (HPF)-based fast-signal generator sharpens the rising edge of the standard SiPM output signal reducing time jitter due to the dark counts of the detector. It is implemented by leveraging the equivalent resistance of the current mirror transistor and the ac-coupling capacitor between the current mirror and the current discriminator to avoid hardware and power consumption overhead. Compared with OFF-chip solutions, the ON-chip approach eliminates the packaging pins and high-speed buffers needed for carrying the fast signals reducing packaging complexity and power consumption of the readout system. The energy quantizer utilizes the SiPM charge integrator as the ADC track-and-hold (T/H) circuit to improve the front-end power efficiency. The fast signal generator and the SAR ADC are implemented in a current-mode application-specific integrated circuit (ASIC) designed in a 0.18-
$\mu \text{m}$
CMOS technology. Measurement results show that the ON-chip fast signal generator is effective in improving the timing performance of the readout system. The timing resolutions are measured using SensL’s
$3\times $
3 mm2 SiPM device with a terminal capacitance of 850 pF using an ultrashort laser pulser. Measurement results show that the fast signal generator improves the timing resolution by 23.4% compared with timing measurement using the standard output signal when the output charge is 300 pC. The ASIC achieved a measured ADC signal-to-noise-distortion ratio (SNDR) of 53.08 dB and a spurious-free dynamic range (SFDR) of 62.74 dB at 1 MS/s and a maximum front-end gain nonlinearity of 3.3% over 20–800-pC input charge range while dissipating 4.1 mW of power from a 1.8-V supply.