Device-Level Thermal Analysis for Gallium Oxide Lateral Field-Effect Transistor

Poor intrinsic thermal conductivity (TC) of beta-phase gallium oxide (
$\beta $
-Ga2O3) poses challenges to the thermal management of its devices. Various packaging-level cooling strategies have been proposed, demonstrating great thermal benefits. In addition, much attention has been paid to the device-level cooling methods, which have shown remarkable efficiency for the thermal management of many wide and ultrawide bandgap devices. As the device-level thermal management efficiency is highly associated with the device architecture, deep insight into the device architecture effect is highly warranted. Here, we used numerical simulation method to conduct the device-level thermal analysis on
$\beta $
-Ga2O3 MESFETs. The impacts of various device components on channel temperature are comprehensively investigated, such as metal geometry, layout alignment, thickness, and orientation-dependent
$\beta $
-Ga2O3 TCs, and the thermal boundary resistance (TBR) between metal and
$\beta $
-Ga2O3. We show that increasing the gate length from 0.5 to
$1.5 \mu \text{m}$
achieves a 35 K reduction in maximum channel temperature, equivalent to optimizing the device’s substrate TC from 100 to 2000 W/mK. Furthermore, properly designing the layout alignment on the 3-D anisotropic
$\beta $
-Ga2O3 substrate could also benefit the thermal dissipation. Particularly, aligning the gate length to the direction at which
$\beta $
-Ga2O3 has the highest and lowest in-plane TC could render
$\sim $
60 K difference in maximum channel temperature. Overall, we analyzed the efficiency of various device-level cooling strategies for the
$\beta $
-Ga2O3 device, suggesting a thermal design route by designing device architecture.