Reconfigurable Stochastic Computing Architecture for Computationally Intensive Applications

The design of computation-intensive and complicated applications is limited by hardware resources. To realize efficient utilization of circuit area with lightweight computational logics and execute optimized operation, we propose an architecture of reconfigurable stochastic computing (SC) unit. The proposed SC unit decodes mathematical formula and reconfigures SC circuits to improve design productivity. Compared to the deterministic implementation, the proposed architecture reduces the circuit area by 39.7%.