The first study of 10nm-class backside defect using Co-Routine based ETL in DRAM

As the critical dimension of the Dynamic Random Access Memory (DRAM) device continues to be reduced, the defect size to be managed in the semiconductor process is gradually decreasing to an extreme level. Samsung Electronics Co. (SEC) continues to upgrade the sensitivity of defect detection power on the front, but the wafer backside defect is managed over 25nm, so the defect less than 25nm has a blind spot for yield and quality control. In this study, we introduce a data pipeline technology that enhances Extract, Transform, and Load (ETL) using defects less than 25nm that existed only as equipment log files in leveling units in the photolithography facility. And the Electrics Die Sorting (EDS) yield reduction rate was derived through the correlation analysis of the killing ratio by backside defect size. Consequently, the yield prediction accuracy of 1zDRAM (8Gb DDR4) in the fabrication was improved by 8.8%, and the 0.3% yield improvement factor was identified. It is also expected to help with backside defect prevention studies on nextgeneration development products.