An Improved Dynamic Latch Comparator with Low Power Consumption for SAR ADC Applications

This paper presents the design of dynamic latch comparator with Adaptive Power Control (APC) technique to have low power consumption for SAR analog-to-digital converter ADC. The proposed comparator consists of a pre-amplifier, latch, and APC structure which helps to reduce the power consumption in the comparator. The proposed comparator achieves a dynamic performance of
$61\mu \mathrm{V}$
offset, 121ps propagation delay, and
$856\mu \mathrm{W}$
power consumption at
$480\text{MHz}$
frequency with 1.
$5\mathrm{V}$
power supply. The developed comparator uses a
$130\text{nm}$
CMOS process technology.