Design Optimization for Decimation Filter for High Performance Sigma-Delta ADC

This paper presents a design optimization method for multistage Butterworth decimation filter for sigma-delta ADC. A new technique for preventing overflows in each stage is also illustrated, which allows to minimize the hardware size and power consumption of the filter implementation, while maintaining a high Signal to Noise and Distortion Ratio (SNDR). We demonstrate with simulation results that the proposed Butterworth Decimation Filter and its implementation, when integrated with a Sigma-delta ADC, can significantly improve the SNDR near the cut off frequency.