Correlation Aware Random Pattern Generation for Test Time and Shift Power Reduction of Logic BIST

Logic built-in self-tests (BISTs) are widely used in the latest industrial circuits, such as automatic ICs. Though logic BIST has the advantage of a low-cost in-field testing, it has problems such as a low fault coverage and a high power consumption. Especially in automotive ICs, it is crucial to achieve a high fault coverage in a limited time that is associated with the test time reduction. A new pattern generation method is proposed for shorter test times and low power tests. Not only considering the weight of logic 1 and 0 for each scan cell, but also considering the correlation of scan cells that have the same logic 1 or 0 to detect faults. Experimental results show the test time reduction and the power reduction during the shift cycle by the proposed method.