Hiding Precharge Operation For Improved SRAM Cycle Time

In this paper, we propose a method to improve SRAM performance by adjusting the operation timing of the internal control signal. By hiding the pre-charge operation first performed in the cycle, the faster SRAM operation is enabled without additional circuitry. In
$16\mathrm{K}$
SRAM implementation based on 28nm CMOS technology, the proposed SRAM design show that the read operation time is reduced by 36.7% and the write operation time is reduced by 13.5%.