A 80-MHz 91.2 ppm/°C Self-Biased Frequency-Locked-Loop Timer

The paper presents an 80-MHz self-biased timer using a frequency-locked loop (FLL) to determine the frequency with PVT compensation. In the FLL, the auto-zeroing technology is employed to cancel out the amplifier offset voltages, thus generating temperature-insensitive resistive current for the switched capacitor. Implemented in 0.18-μm CMOS, the FLL clock generator provides the output frequency depending upon the passive components and divider ratio. The measured temperature stability for the oscillator is about 91.2 ppm/°C from 10°C to 110°C and supply sensitivity is 69.78 %/V from 0.81V to 1V.