Analysis of Impacting Multi-stack Standard Cells on Chip Implementation

As the process node shrinks, the architecture of large size standard cells is changing, from single-row-height to multi-row-height to keep the cells' geometric shape close to square. Today, using a mixture of single-row-height and multi-row-height cells becomes a common adoption for implementing chips below 15nm technology. In this paper, we scrutinize an alternative architecture of standard cells, called multi-stack standard cells, which in some aspects is able to provide competitive strengths against the architecture of multi-row-height cells. Precisely, through logical analyses and supporting data, we answer the following two questions: (1) What are the structural and metal usage differences between the multi-stack and multi-row-height cells? (2) What kind of chip implementation requirements can the multi-stack cells make it easier to meet than the multi-row-height cells?