TCLink: A Fully Integrated Open Core for Timing Compensation in FPGA-Based High-Speed Links

The high luminosity expected in the second phase of the upgrades of the Large Hadron Collider (LHC phase-2 upgrades) will pose unprecedented challenges to its four experiments in terms of collisions density—also known as pile-up—per beam crossing. Disentangling the vertices of 200 simultaneous collisions every 25 ns requires high granularity in the detectors, as well as extremely precise and stable timing. While short-term timing stability is usually a concern addressed in timing distribution systems, long-term variations due to changing environmental conditions can accumulate through distribution chains and can dominate the overall timing stability of the systems they serve. Timing distribution systems in LHC experiments typically use high-speed links and clock recovery. This article presents a logic core that can be used to mitigate long-term temperature variations in high-speed links. The timing compensated link (TCLink) is an open-source firmware core fully integrated in Xilinx Ultrascale Field Programmable Gate Arrays (FPGAs). It demonstrates picosecond-level phase precision over timing distribution systems, improving the overall timing stability in physics experiments.