Analysis of time-interleaved delta-sigma analog to digital converter

Although /spl Delta//spl Sigma/ modulators are widely used for low to moderate rate analog-to-digital conversion, the time oversampling requirement has limited their application to higher rate converters. This paper presents an architecture wherein multiple /spl Delta//spl Sigma/ modulators are combined with time-interlacing. Indeed, the system achieves the effect of oversampling from the multiplicity of /spl Delta//spl Sigma/ modulators. For a system containing M L/sup th/ order /spl Delta//spl Sigma/ modulators, approximately L bits of accuracy are gained for every doubling of M. A major benefit of the architecture is that it retains much of the robustness to non-ideal circuit behavior of individual /spl Delta//spl Sigma/ modulators. As a result, the architecture offers the potential of integrating high-precision, high-speed ADC together with digital signal processing functions using VLSI processes optimized for digital circuitry. Because of the parallelism, the performance of the architecture is hugely degraded by channel mismatches. A digital technique is used to overcome this problem. The paper presents the general architecture and provides a performance analysis closely supported by computer simulations.