Design and FPGA Implementation of the LUT based Sigmoid Function for DNN Applications

Nowadays deep learning algorithms are became popular in the field of biomedical applications for automatic classification and detection problems. There are multiple issues in implementing these algorithms on digital platform. The major issue is it requires a dedicated hardware to meet the low power requirements in real-time. Hence, the low power hardware accelerators for deep neural network (DNN) classifiers is developed in this work to cope the above issue. In a DNN, activation function is important in feature classification. In this work, an area efficient digital architecture for evaluating the sigmoid function is also proposed and its resource requirements reported. The proposed architecture took the advantage of symmetry of sigmoid function and save 50% of the storage area. The performance of the proposed architecture is assessed by separately employing the proposed sigmoid and theoretical sigmoid blocks in a simple Convolution Neural Network (CNN) and observed that the model with quantized processing achieved the accuracy close to the model performance with traditional sigmoid block.