Process Optimizations for Ge-On-Si Depletion Mode Transistors Using Mesa Architecture

The p-Ge layers are epitaxially grown by MBE over the n-Ge and strain-free Ge buffer layers on the Si substrate. The drain-source & channel mesa is patterned in the p-Ge layer to create the raised active channel. Post-plasma oxidation was carried out to improve the interface properties of Ge channel. The proposed process doesn't involve source-drain implants, ease channel patterning using MAPDST, a -ve tone resist with high etch resistance and selectivity w.r.t. Ge. The process flow scheme will utilize the “beyond Si” channel materials over Si substrates, concurrently exploiting the standard well, established state-of-art Si CMOS fabrication technology.