A Power-Proportional, Dual-Bandwidth, and Constant-Delay Receiver Front-End for Energy-Efficient Dual-Rate Optical Links

This article presents a dual-bandwidth front-end (FE) for a rapidly reconfigurable dual data rate and power-proportional optical receiver. The proof-of-concept receiver FE is capable of operation at 8- and 4-Gb/s data rates. Implemented in 65-nm CMOS technology, the proposed FE consists of a shunt-feedback transimpedance amplifier (TIA), a configurable one-stage-to-three-stage postamplifier (PA), and an offset compensation (OC) loop. By reconfiguring the number of stages in the PA, the FE maintains a near-constant delay when its bandwidth is changed. This allows synchronization to be maintained, with limited bit errors when the target data rate is switched. The prototype receiver was measured with an optical input at 8 and 4 Gb/s. The overall FE dissipates 6.12 mW at 8 Gb/s (0.76 pJ/bit) and 2.86 mW at 4 Gb/s (0.72 pJ/bit). The measured receiver optical sensitivities for 8- and 4-Gb/s inputs at high-bandwidth (HBW) and low-bandwidth (LBW) modes are −7.7 and −9.8 dBm, respectively. The measurement results confirm the matched delay through the FE with delay variations within 8 ps.