DDR4 Ball Grid Array Package Intermittent Fracture Effect on Signal Integrity

Double data Rate type 4 memory (DDR4) die are commonly packaged in ball grid array (BGA) packages. The package solder balls develop fractures due to difference in the thermal coefficient of expansion of the package and printed circuit board (PCB). The intermittent behavior of the fracture is due to the momentarily opening of the solder joint due to vibration or the warpage of the package and the PCB. This intermittent behavior can result in no fault found phenomenon in memory systems. DDR4 response in the presence of an intermittent fracture depends on the location of defect. The defect can occur in clock, address, or data channel. A test fixture is used to show the ac coupling nature of fracture in BGA package solder ball. The intermittent change in the height of fracture is analyzed using 3-D electromagnetic model of the solder ball using high-frequency structure simulator (HFSS) software. HFSS model of the fractured solder ball is used along with DDR4 channel topology to compare the sensitivity of clock, address, and data channel response to intermittent fracture. It is shown that the data channel is most sensitive to intermittent fracture. DDR4 data mask violation occurs for even a small fracture height of 0.1
$\mu \text{m}$
. For clock channel, the eye degrades or becomes smaller as the fracture height increases from 0.1 to 3
$\mu \text{m}$
, but even for 3-
$\mu \text{m}$
fracture height, clock eye diagram remains within DDR4 clock ±110 mV specification. For address channel, the eye degrades or becomes smaller when the height of fracture increases from 0.1 to 3
$\mu \text{m}$
. For fracture height of 3
$\mu \text{m}$
, DDR4 address ±65-mV input specification violation occurs. Address channel is more sensitive to intermittent fracture as compared to clock channel. The analysis shows that there is always intermittent error in data channel due to intermittent fracture, and there are more intermittent errors in address channel compared to clock channel.