SDR Implementation of A Broadband Digital Predistorter with Parallel LUT Structure

This paper presents a wide-band digital predistorter using software-defined radio (SDR) architecture with a parallel look-up table (LUT) structure. The proposed scheme indexes multiple samples in a single clock cycle, which not only reduces DSP resource consumption, but also extends the bandwidth of conventional serial DPD to a higher rate, without being limited by the maximum clock rate. The corresponding digital predistortion (DPD) model is based on the generalized memory polynomial (GMP). Indirect learning and regularization method are also applied to make coefficients identification stable. The whole system can perform real-time DPD iterations, without commercial equipment as PC or Matlab. A 4.9GHz GaN Doherty power amplifier (DPA) MMIC module is used to validate the predistorter with a 100-MHz bandwidth signal. The results show good linearization performances with the adjacent channel power ratio (ACPR) below -48 dBc, meeting the requirements of the 5G communication standard.