Compact and Broadband ESD Protection I/O Pad Using Pad-Stacked Inductor

In this paper, a compact and broadband electrostatic discharge (ESD) protection input/output (I/O) pad for high-speed interfaces is designed and miniaturized using a pad-stacked inductor in a 28-nm CMOS technology. A
$\pi $
-diode with a single inductor is adopted to compensate for the parasitic capacitance and extend the bandwidth of ESD-protected I/O pad. To minimize the increase of the chip area by the inductor, the pad-stacked inductor is proposed, where the inductor is placed below I/O pad. The eddy current, then, is induced in the I/O pad by time-varying magnetic field by the inductor, degrading the performance of the inductor, such as the reduced inductance, increased resistance and capacitance. These effects are thoroughly investigated using the developed equivalent circuit model which is also utilized to design the pad-stacked inductor. The compact and broadband
$\pi $
-diode with the reduced eddy current is then designed by the proper selection of the inductor layer and a patterned I/O pad. Measurement of the designed
$\pi $
-diode with the pad-stacked inductor exhibits broadband impedance match and insertion loss, that is, a return loss better than 10 dB up to 26.5 GHz and a 3-dB bandwidth as large as 22.9 GHz. The chip area of the
$\pi $
-diode remains the same as that of the I/O pad thanks to the proposed pad-stacked inductor. Therefore, the designed
$\pi $
-diode can be applied for the compact high-speed I/O interface circuits.